An integrated circuit employing synchronous logic may include thousands of units (“syncs”) such as logic macros, registers, latches, and flip-flops that are clocked by a clock signal. Macros that are created using synthesis frequently include spare latches that can be used with metal-only electronic circuits on a microprocessor. In creating these macros, the synthesis process displays no preference in placing these spare latches since they have no timing critical paths. In the past it has been observed that these latches can end up in clusters rather than distributed. To be of use for electronic circuits it is necessary to make sure that the spare latches are evenly distributed throughout the macro.
Currently, to solve this problem, engineers manually go into each macro and visually inspect the placement. Obviously, this is tedious and cumbersome.
There is a need for a better latch placement method to overcome the shortcomings of the prior art.